This invention pertains to PLL (Phase-Locked Loop) technology. In particular, this invention pertains to a type of PLL circuit that can remove the ripple component from the output signal for the PLL circuit of a fractional frequency division system.
A cellular phone is a multiple frequency channel access system. In order to shift the frequency in use to an idle channel, a PLL circuit that allows high-speed lockup is needed.
In FIG. 5, 101 represents a PLL circuit with a fractional frequency division system, prior art for the PLL circuit.
This PLL circuit 101 is placed in a semiconductor integrated circuit device that forms the transceiver of a cellular phone. It is composed of oscillator 131, frequency divider 132, reference signal generator 133, phase comparator 134, charge pump circuit 135, low-pass filter 136, controller 138 and compensating circuit 137.
Oscillator 131 generates an oscillation signal at a frequency corresponding to the signal output from low-pass filter 136, and outputs the oscillation signal to the output terminal. The oscillation signal is output as external output signal OUT to both frequency divider 132 and to the other circuits in the semiconductor integrated circuit device where PLL circuit 101 is arranged.
Frequency divider 132 performs frequency division for the oscillation signal input to it from oscillator 131, generates comparison signal V, and outputs it to phase comparator 134. Also, reference signal generator 133 outputs reference signal R at a prescribed frequency to phase comparator 134.
As illustrated by the timing chart shown in FIG. 6, phase comparator 134 rises in synchronization with the rise of comparative signal V and reference signal R, respectively, and, when reference signal R falls, it outputs output signals D and U in synchronization with the fall of reference signal R.
Output signals U and D of phase comparator 134 are output to charge pump circuit 135.
FIG. 9 is a diagram illustrating the constitution of charge pump circuit 135. This charge pump circuit 135 has output terminal 185, source-side constant current circuit 171, sink-side constant current pump circuit 172, source-side switch circuit 181, and sink-side switch circuit 182.
When phase comparator 134 outputs output signals U and D, respectively, output signals U and D are input to source-side switch circuit 181 and sink-side switch circuit 182, respectively.
Source-side switch circuit 181 and sink-side switch circuit 182 have upper and lower operation transistors 175 and 177, upper and lower stand-by transistors 174, 176, and inverters 178 and 179, respectively.
Stand-by transistors 174 and 176 and operation transistors 175 and 177 are all MOS transistors. Stand-by transistor 174 and operation transistor 175 that form source-side switch circuit 181 have their source terminals connected to each other. Similarly, stand-by transistor 176 and operation transistor 177 of sink-side switch circuit 182 are also connected to each other.
The common connection portions of stand-by transistors 174, 176 with operation transistors 175, 177 are respectively connected to source-side constant current circuit 171 and sink-side constant current circuit 172.
The gate terminal of upper stand-by transistor 174 and the gate terminal of lower operation transistor 177 are directly connected to the two output terminals of phase comparator 134, respectively, and output signals U and D are input as is. On the other hand, the gate terminal of upper operation transistor 175 and the gate terminal of lower stand-by transistor 176 are connected through inverters 178 and 179 to the two output terminals of phase comparator 134, respectively, and the inverted signals of output signals U and D are input. The constitution is such that for stand-by transistors 174, 176 and operation transistors 175, 177 of source-side switch circuit 181 and sink-side switch circuit 182, when one side is ON, the other side is OFF.
Suppose lower operation transistor 177 is ON, while upper operation transistor 175 is OFF. In this state, only sink-side constant current circuit 172 is connected to output terminal 185, and constant current CD generated by sink-side constant current circuit 172 (hereinafter referred to as sink-side constant current) is sunk at output terminal 185.
Suppose upper operation transistor 175 is ON, while lower operation transistor 177 is OFF. In this state, constant current CU generated by source-side constant current circuit 171 (hereinafter referred to as source-side constant current) is output from output terminal 185.
When output signals U and D are both in xe2x80x9cLxe2x80x9d state, xe2x80x9cLxe2x80x9d is input to the gate terminal of upper stand-by transistor 174, and xe2x80x9cHxe2x80x9d that is obtained by inversion using inverter 178 is input to the gate terminal of upper operation transistor 175. Because both upper operation transistor 175 and upper stand-by transistor 174 are P-channel MOS transistors, upper operation transistor 175 is OFF, while upper stand-by transistor 174 is ON, and constant current CU supplied by source-side constant current circuit 171 flows through upper stand-by transistor 174 to ground potential.
On the other hand, xe2x80x9cHxe2x80x9d that is obtained by inversion using inverter 179 is input to the gate terminal of lower stand-by transistor 176, and xe2x80x9cLxe2x80x9d is input to the gate terminal of lower operation transistor 177. Because both lower stand-by transistor 176 and lower operation transistor 177 are N-channel MOS transistors, lower operation transistor 177 is OFF, while lower stand-by transistor 176 is ON, and constant current CD supplied by sink-side constant current circuit 172 flows through lower stand-by transistor 176 at ground potential. Consequently, constant currents CU and CD do not flow at output terminal 185.
In this state, when output signals U and D are inverted from xe2x80x9cLxe2x80x9d to xe2x80x9cH,xe2x80x9d stand-by transistors 174 and 176 are turned OFF, and, at the same time, operation transistors 175 and 177 are turned ON.
Output signals U and D rise independently in synchronization with the rise of reference signal R and comparison signal V of the preceding stage, respectively. When upper operation transistor 175 alone is ON, source-side constant current CU is output from output terminal 185, lower operation transistor 177 alone is ON, and sink-side constant current CD is sunk at output terminal 185. Also, because the magnitudes of the current supply of source-side constant current source 171 and sink-side constant current source 172 are equal to each other, and the current values of constant currents CU and CD are nearly equal to each other, when operation transistors 175 and 177 are ON at the same time, no current flows at output terminal 185.
Then, when reference signal R falls from xe2x80x9cHxe2x80x9d to xe2x80x9cL,xe2x80x9d output signals D and U fall at the same time, so that operation transistors 175 and 177 are turned OFF at the same time, and, as shown in the timing chart of FIG. 6, the supply of constant currents CU and CD is always terminated at the same time ts.
As explained above, after output signals U and D are converted from xe2x80x9cLxe2x80x9d to xe2x80x9cH,xe2x80x9d respectively, during the period of conversion from xe2x80x9cLxe2x80x9d to xe2x80x9cH,xe2x80x9d only one of constant currents CU and CD, output, respectively, from source-side constant current source 171 and sink-side constant current source 172, flows at the output terminal of charge pump circuit 135. This current is represented by SS in FIG. 6.
This current SS is output to low-pass filter 136. Low-pass filter 136 outputs said current SS to oscillator 131 after removing its high-frequency component.
The frequency of the oscillation signal of oscillator 131 is changed in correspondence with the voltage value output from low-pass filter 136. Said oscillator 131, frequency divider 132, reference signal generator 133, phase comparator 134, charge pump circuit 135, and low-pass filter 136 form a negative feedback loop. This negative feedback loop operates such that the phase difference becomes smaller, that is, the phase of comparison signal V comes into agreement with the phase of reference signal R. As a result, the frequency of external output signal OUT takes on the value obtained by multiplying the frequency of the reference signal by the frequency division value of frequency divider 132.
The frequency division value of said frequency divider 132 is controlled by controller 138, the frequency division value is changed periodically, and the frequency of external output signal OUT is locked at the value of the average frequency division value times the frequency of the reference signal.
For example, supposing the target frequency to be 1000025 kHz, if the reference signal has a frequency of 200 kHz, one may select the frequency division value for 7 periods (35 xcexcsec) to be 5000, and the frequency division value for 1 period (5 xcexcsec) to be 5001. In this case, the average frequency division value for the 8 periods is 5000.125 (=5000+xe2x85x9). In this case, the frequency of external output signal OUT is locked at the average frequency division value, that is, 5000.125 (=5000+xe2x85x9), times the frequency of the reference signal (200 kHz), that is, at the target frequency of 1000025 kHz.
In this way, if the average frequency division value is a value having this decimal part, it is possible to utilize high frequencies of 800 MHz, 1 GHz, etc. with narrow channel intervals of 25 kHz, 12.5 kHz, etc.
However, when the frequency division value is changed periodically as explained above, even after the external output signal OUT comes into agreement with the target frequency, the frequency division value of frequency divider 132 still varies periodically. Consequently, the phase of comparison signal V and the phase of reference signal R are not completely in agreement with each other, and a phase difference is generated. Due to this phase difference, the signal output from phase comparator 134 contains a ripple current that varies periodically.
The ripple current contained in the signal output from phase comparator 134 generates a spurious component in external output signal OUT, which not only degrades the reception characteristics of cellular phones and other communication equipment, but also interferes with communication. Consequently, this is a significant problem.
Compensating circuit 137 is arranged in said PLL circuit 101. The amount of charge of a prescribed ripple current is stored in compensating circuit 137 and, when a control signal is input from controller 138 to compensating circuit 137, at the input timing of this control signal, a charge that has the same magnitude as the amount of charge of the ripple current, yet has an opposite sign, is superimposed on the output signal of charge pump circuit 135, so that the ripple current can be canceled. As a result, control is achieved such that no spurious component is superimposed on external output signal OUT.
However, it is still impossible to remove the spurious component completely from external output signal OUT even when said compensating circuit 137 is used.
The present inventors of this invention performed research on the reasons for superimposition of the spurious component on external output signal OUT, and have found this reason.
FIGS. 7 and 8 illustrate the relationship between constant current CU output from charge pump circuit 135 and constant current CD sunk into it.
For said PLL circuit 101, because its frequency division value varies periodically, upper operation transistor 175 is ON for prescribed periods, and, as shown in FIGS. 7 and 8, ON start time t177 of lower operation transistor 177 is earlier or later than ON start time t175 of upper operation transistor 175. FIG. 7 illustrates the state when it is earlier, and FIG. 8 illustrates the state when it is later. In this way, due to fractional frequency division, one of operation transistors 175 and 177 turns ON earlier or later than the other one, yet such a deviation in ON start time is a miniscule one similar in degree to generation of the ripple current. As a result, the operation transistor that turns ON earlier affects ON of the operation transistor that turns ON later, and the operation for obtaining output signals D and U of phase comparator 134 is not performed. Consequently, the output signal of charge pump circuit 135 contains an error component other than the ripple current.
As a result, even when a compensating charge is superimposed by compensating circuit 137, it is still impossible to remove the error component. It has been found that because the error component results each time phase comparison is performed, it appears periodically in the output signal of charge pump circuit 135, and, as a result, a spurious component is superimposed.
A purpose of this invention is to solve the problems of the conventional methods by providing a technology that does not have a spurious component superimposed on the output signal of the PLL circuit.
In accordance with one aspect of, this invention, a PLL circuit comprises an oscillator that outputs an oscillation signal at a frequency corresponding to a control signal, a frequency divider of a fractional frequency division system that divides and outputs the oscillation signal, a reference signal generator that generates a reference signal, a phase comparator that compares the phase of the signal output from said frequency divider and that of the reference signal and outputs a first signal and a second signal corresponding to the phase difference, a charge pump circuit that has a first current supply circuit, which supplies to the output terminal a first current corresponding to the first signal, and a second current supply circuit, which supplies to the output terminal a second current corresponding to the second signal, a capacitive element that is connected to the output terminal of the charge pump circuit, a low-pass filter that takes the signal from the output terminal of the charge pump circuit as its input and supplies the control signal to the oscillator, a switch element that is connected between the output terminal of the charge pump circuit and the input terminal of the low-pass filter, and a compensating circuit that supplies a compensating current to the input terminal of the low-pass filter for removing the ripple component contained in the signal of the output terminal of the charge pump circuit; when the PLL circuit is in the locked state, supply of the first current and supply of the second current start at different times, and these supplies are stopped at the same time.
Also, for the PLL circuit in this invention, it is preferred that the switch element be in the OFF state when the first current or second current is supplied.
Also, the following aspect is preferred: the first current supply circuit has a first constant current source and a second constant current source, the second current supply circuit has a third constant current source, and current supply of the second constant current source starts after a prescribed time delay following the starting time of current supply by the first constant current source.
In addition, for one aspect of the PLL circuit in this invention, it is preferred that it have a controller that controls current supply of the second constant current source in correspondence with the reference signal.
Also, the following aspect is preferred: the phase comparator has a first logic circuit that takes the reference signal as its input and outputs the first signal, a second logic circuit that takes the output signal of the frequency divider as its input and outputs the second signal, and a third logic circuit that resets the first and second logic circuits in response to the reference signal; the first current supply circuit has a first transistor that connects the first constant current source to the output terminal in response to the first signal, and a second transistor that connects the second constant current source to the output terminal in response to the output signal of the controller; and the second current supply circuit has a third transistor that connects the third constant current source to the output terminal in response to the second signal.
In addition, in one aspect of the invention, it is preferred that the circuit have a frequency division value controller that controls the fractional frequency division value of the frequency divider and the compensating circuit.
According to another aspect of this invention, the current supply period is set such that, in the charge pump circuit arranged in the PLL circuit, the amount of charge per unit time supplied from the sink-side constant current circuit (second constant current supply circuit) to the control terminal and the amount of charge per unit time supplied from the source-side constant current circuit (first constant current supply circuit) to the output terminal have different magnitudes.
For example, supposing the source-side constant current circuit and sink-side constant current circuit are formed such that each of them has a constant current source and an operation transistor, and, when an operation transistor is ON, the corresponding constant current source is connected to the control terminal, and when it is OFF, the corresponding constant current source is turned OFF from the output terminal, we will look at the case when the operation transistors of both the source-side constant current circuit and the sink-side constant current circuit are OFF at the same time. In this case, when the frequency of the output signal of the oscillator is stable, the total amount of charge sourced by the source-side constant current circuit to the output terminal is equal to that sunk by the sink-side constant current circuit at the output terminal. However, because the operation transistors are OFF at the same time, if the amount of charge per unit time sourced by the source-side constant current circuit to the output terminal is different from that sunk by the sink-side constant current circuit during the current supply period, it is possible for the ON start times of the operation transistors to be different from each other. For operation transistors in the prior art, the transistor that turns ON earlier affects the operation of the transistor that turns ON later. However, by setting an appropriate deviation period, it can be arranged that the operation transistor that turns ON earlier will have no influence on the operation transistor that turns ON later. As a result, the error component due to the charge pump circuit is not contained in the output of the output terminal, and only the charge corresponding to the ripple current component is output from the output terminal. Consequently, by determining the amount of charge of the ripple current beforehand and by superimposing at the output terminal a charge with opposite sign to that of the ripple current, one can completely eliminate the ripple current.
Also, according to an aspect of this invention, the constitution is such that one or both of the source-side and sink-side constant current circuits has [or have] plural constant current sources, and it is possible to change the number of constant current sources connected to the output terminal. With this constitution, it is possible to change the amount of charge per unit time supplied to the output terminal during the current supply period. For example, assuming that the number of constant current sources connected to the output terminal is reduced during a certain period while it is increased during the remaining period, one can supply a smaller amount of charge to the output terminal during the control period, and supply a larger amount of charge after the deviation period. Conversely, one may also supply a larger amount of charge to the control terminal at first, and then supply a smaller amount of charge to the control terminal.
By having the switch element turned OFF during the period that charge flows from the output terminal, the charge supplied to the output terminal is used to charge the capacitive element instead of being directly input to the low-pass filter.
By turning on the switch element after charge is no longer supplied to the output terminal, the charge on the capacitive element is discharged, and is input to the low-pass filter. However, the accumulated charge becomes equal to the amount of charge of the ripple current component. As explained above, when a charge of sign opposite to that of the ripple current is superimposed at the input terminal of the low-pass filter, one can essentially completely eliminate the ripple current and have a zero ripple charge input to the low-pass filter.